FP6 priority

1.1.2   Information Society Technologies

1.2.3

Title of the proposal

Testability of System on Chip Design

Institute

Slovak Academy of Sciences, Institute of Informatics
Dubravska cesta 9, 842 37 Bratislava, Slovak Republic

Contact

Research subject for a potential FP6 project

The proposed research subject is test methods of System on Chip (SoC) design, mainly in the areas:
- Built-in self-test techniques for digital modules, memories and
- Defect-oriented test pattern generation and fault simulation algorithms.
The objective of the research are testability issues of SoC design. Solved problems are:
- investigation on real defect coverage of digital circuits,
- development and implementation of advanced test pattern generation algorithms,
- fault modeling and fault simulation techniques for digital circuits,
- development and application of logic and memory built-in self-test techniques for digital IP cores,
- standard application (IEEE 1149.1, P1500) for SoC and IP cores, and
- developing test approaches for interconnections and interfaces.
Mentor Graphic and XILINX CAD tools are used in practical experiments.

Recent international cooperation of the research team

Fraunhofer Institute for Integrated Circuits, Dresden, Germany; Linkoping University, Linkoping, Sweden; Darmstadt University of Technology, Germany; Tallinn Technical University, Estonia; Warsaw University of Technology, Poland; Institute of Electron Technology, Warsaw, Poland; IMEC, Leuven, Belgium; Ilmenau Technical University, Germany; Universite Joseph Fourier, Grenoble, France; Eidhoven University of Technology, the Netherlands; Technical University of Liberec, Czech republic; University of Ljubljana, Slovenia; Riga Technical University, Latvia; Kaunas University of Technology, Lithuania;

Proposer´s relevant publications related to the research subject

1. A. Schneider, E. Ivask, P. Miklos, J. Raik, K.H. Diener, R. Ubar, T. Cibakova, E. Gramatova: Internet-based Collaborative Test Generation with MOSCITO. Proc. of 2002 Design, Automation and Test in Europe Conference and Exhibition (DATE’02), Paris, France, March 2002, pp.221-226.

2. J. Stefanovic, P. Miklos, E. Gramatova: A New Open Platform for VHDL Modelling on Behavioural Level, Proc. of the 4th IEEE Design and Diagnostics of Electronics Circuits and System Workshop (DDECS’01), Gyor, Hungary, April 2001, pp. 141-144.

3. T. Cibakova, M. Fischerova, E. Gramatova, W. Kuzmicz, W. Pleskacz, J. Raik, R. Ubar: Defect-Oriented Test Generation Using Probabilistic Estimation. Proc. of the 8th International Conference on MIXDES 2001, Zakopane, Poland, June 2001, pp. 131-136.